### Working Of The System

For the working of Frequency multiplier circuit the frequency divider is inserted between the VCO and phase comparator. Since the output of the divider is locked into the input frequency f_{IN}, the VCO is actually running at a multiple of the input frequency. The desired amount of multiplication can be obtained by selecting a proper divide-by-N network, where N is an integer. For example, to obtain the output frequency f_{OUT} = 5f_{IN}, a divide-by-N = 5 network is needed. Figure 1-1 shows the function performed by a 7490 (4-bit binary counter) configured as a divide-by-5 circuit. In this figure, transistor Q_{1} is used as a driver stage to increase the driving capability of the NE565.

### Circuit Description of frequency multiplier

To verify the operation of the circuit frequency multiplier, one must determine the input frequency range and then adjust the free-running frequency f_{OUT} of the VCO by mean of R_{1} and C_{1} so that the output frequency of the 7490 divider is midway within the predetermined input frequency range. The output of the VCO now should be 5f_{IN}. The output frequency f_{OUT} can be adjusted from 1.5 KHz to 15 KHz by varying potentiometer R_{1} (f_{OUT} = 1.2/4R_{1}C_{1}). This means that the input frequency f_{IN} range has to be within 300 Hz to 3 KHz. In addition, the input waveform can either be sine or square wave and may be applied to input pin 2 or 3.

Even though supply voltages of ±10 V are used in figure 1-1, the NE565 can be operated on ±5 supply voltage instead. A small capacitor C_{3} typically 1000pF, is connected between pins 7 and 8 to eliminate possible oscillations. Also, capacitor C_{2} should be large enough to stabilize the VCO frequency.

### PARTS LISTS

**Resistors (all ¼-watt, ± 5% Carbon)**

R_{1} = 20 KΩ potentiometer

R_{2} = 2 KΩ

R_{3} = 4.7 KΩ

R_{4} = 10 KΩ

#### Capacitors

C_{1} = 0.01µF

C_{2} = 10 µF

C_{3} = 0.01 µF

#### Semiconductors

IC_{1} = NE565

IC_{2} = 7490 4-bit binary counter

Q_{1} = 2N3391

i want to make an induction furnace pl give me a practical circuit for the same.

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i want to do this circuit using FPGA

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