Working Of The System
For the working of Frequency multiplier circuit the frequency divider is inserted between the VCO and phase comparator. Since the output of the divider is locked into the input frequency fIN, the VCO is actually running at a multiple of the input frequency. The desired amount of multiplication can be obtained by selecting a proper divide-by-N network, where N is an integer. For example, to obtain the output frequency fOUT = 5fIN, a divide-by-N = 5 network is needed. Figure 1-1 shows the function performed by a 7490 (4-bit binary counter) configured as a divide-by-5 circuit. In this figure, transistor Q1 is used as a driver stage to increase the driving capability of the NE565.
Circuit Description of frequency multiplier
To verify the operation of the circuit frequency multiplier, one must determine the input frequency range and then adjust the free-running frequency fOUT of the VCO by mean of R1 and C1 so that the output frequency of the 7490 divider is midway within the predetermined input frequency range. The output of the VCO now should be 5fIN. The output frequency fOUT can be adjusted from 1.5 KHz to 15 KHz by varying potentiometer R1 (fOUT = 1.2/4R1C1). This means that the input frequency fIN range has to be within 300 Hz to 3 KHz. In addition, the input waveform can either be sine or square wave and may be applied to input pin 2 or 3.
Even though supply voltages of ~+mn~10 V are used in figure 1-1, the NE565 can be operated on ~+mn~5 supply voltage instead. A small capacitor C3 typically 1000pF, is connected between pins 7 and 8 to eliminate possible oscillations. Also, capacitor C2 should be large enough to stabilize the VCO frequency.
Resistors (all ¼-watt, ~+mn~ 5% Carbon)
R1 = 20 KΩ potentiometer
R2 = 2 KΩ
R3 = 4.7 KΩ
R4 = 10 KΩ
C1 = 0.01µF
C2 = 10 µF
C3 = 0.01 µF
IC1 = NE565
IC2 = 7490 4-bit binary counter
Q1 = 2N3391